Conceptual render: an open gold-anodised space electronics module with an FPGA, stacked flash and optical fibres, Earth reflected in its window.

Example project · UC 02

Capture more of orbit. Downlink what matters first.

An example project for an Earth-observation payload. Imagery arrives over SpaceFibre, is compressed to CCSDS 123, stored with ECC and scrubbing, and framed for downlink in priority order.

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Conceptual illustration

The problem

Imagers capture far more data than a ground pass can bring down.

Earth-observation instruments produce data much faster than downlink windows allow. The payload recorder has to compress without losing science value, store data safely through radiation effects, and decide what goes down first. The prompt is short, but SIGPT reads it as a full space data chain built from the Space IP suite.

OutcomeA recorder that ingests imagery, compresses it, stores it with error protection and prepares prioritised CCSDS frames for downlink.
TargetAMD Xilinx FPGA confirmed for each project. Flight-grade device selection, radiation qualification and mission certification are separate and are not provided by the Remote FPGA Lab.

The prompt

The simple prompt
Design an FPGA-based satellite payload recorder that receives Earth-observation imagery, compresses it, stores it reliably and prepares prioritized data for downlink.

An example request. Compatibility and availability are confirmed for each selected configuration.

RequirementsRead from the prompt

What SIGPT reads into it.

The prompt is a single sentence. SIGPT expands each verb into a requirement and maps it to the space IP suite.

01 · “Receives”

SpaceFibre ingest

High-rate imagery from the instrument over SpaceFibre, with link-level retry and virtual channels.

02 · “Compresses”

CCSDS 123 compression

Lossless or near-lossless compression for multispectral and hyperspectral imagery. CCSDS 121 and 122 are also available.

03 · “Stores”

Mass memory

An EDAC-protected DDR buffer and NAND flash storage through an ONFI controller with LDPC ECC.

04 · “Reliably”

Fault tolerance

Configuration scrubbing, TMR voting and a fault-tolerant RISC-V for control and recovery.

05 · “Prioritized”

Downlink scheduler

Generated logic that orders stored products by priority class, age and value, under ground control.

06 · “Downlink”

CCSDS framing and coding

AOS data link framing and LDPC channel coding, ready for the transmitter. Command and telemetry use SpaceWire RMAP.

ArchitectureConceptual

A simple conceptual architecture.

Satellite Payload RecorderConceptual block diagram · not a delivered netlist
ExternalReusable IPGenerated logic
Good to know. Compression ratios, storage capacity and downlink throughput depend on the imagery, NAND devices and link budget. Lab testing proves function on a commercial Xilinx board. It is not radiation testing or flight qualification.
FirmwareImplicit with RISC-V

A RISC-V in the design. Firmware built in.

The prompt doesn’t mention a processor, but storing data reliably needs one. SIGPT picked a fault-tolerant RISC-V, and that makes the firmware implicit. Unlike the data logger, this prompt describes real behaviour, so the firmware goes beyond the standard stack.

Always generated

Standard firmware stack

  • Boot and startup codeReset vector, clock and memory setup, linker script
  • Board support packageRegister headers and interrupt map, from the same spec as the RTL
  • A driver for every selected IPInit, read, write, interrupt and DMA hooks
  • Bring-up self-testChecks each peripheral and memory at power-on
  • UART console and JTAG debugStatus, register peek and poke, and logs
  • Build filesMakefile and standard RISC-V GCC toolchain
Added from this prompt

Payload behaviour from the prompt

  • compresses itCompression job control: band setup, mode and per-image metadata
  • stores it reliablyNAND file catalogue, bad-block handling, EDAC and scrub monitoring
  • prioritized dataDownlink scheduler: priority classes, ageing, ground override over RMAP
  • for downlinkAOS virtual-channel mapping and telemetry packets
  • Space-grade defaultsFault-tolerant boot, watchdog and FDIR tasks, because the selected core is fault-tolerant
Firmware follows the prompt. Each verb you write becomes a firmware task, and anything you leave out stays standard. To control it more closely, add detail, for example: keep 72 hours of imagery, downlink cloud-free scenes first.

IP needed

What SIGPT would assemble.

Selected from 140+ 3rd-party FPGA-proven IPs. Drawn mostly from the 24-IP space suite.

Space IP suite · linksSpaceFibre controller IP, SpaceWire RMAP IP
Space IP suite · compressionCCSDS 123 hyperspectral image compression IPCCSDS 121 / 122 as alternatives
Space IP suite · downlinkCCSDS AOS data link IP, CCSDS LDPC encoder IP
Space IP suite · fault toleranceFault-tolerant RISC-V, EDAC memory controller, configuration scrubbing, TMR voter IP
NVMe & storageONFI NAND flash controller IP, NAND flash LDPC ECC IP
Generated firmwareStandard stack with fault-tolerant boot and drivers for SpaceFibre, CCSDS, NAND and RMAP, plus compression control, storage catalogue, priority scheduler and FDIRImplicit with RISC-V · behaviour from the prompt · details
Generated logicDownlink priority scheduler, storage catalogue, integrity monitor and telemetry

Validation steps

How it would be proven on hardware.

Board validation is its own milestone, separate from bitfile generation. Any results are measured on your setup, and none are shown here.

No board? Use the Remote FPGA Lab. Ask for a custom lab setup with a SpaceFibre loopback and a NAND module, then replay recorded imagery through the chain remotely. Remote Lab →
  1. Program the bitfile, load the generated firmware, then replay reference Earth-observation imagery over SpaceFibre.
  2. Decompress on the ground side and check the output bit-exact for lossless mode.
  3. Write to NAND and read back, then check the ECC-corrected error counts and scrubbing status in telemetry.
  4. Command priority changes over SpaceWire and confirm the downlink order follows them.
  5. Verify AOS frames and LDPC-coded output against a reference decoder and the agreed acceptance criteria.
NextAfter the lab

From lab proof toward flight.

Functional proof in the lab is the first step. Flight programmes add device selection, radiation analysis and qualification, which are planned with you.

FPGA productionLicense the bitfile or buy the full project sourceFor deployment on your registered devicesLicensing →
Your own IPAdd your own proven instrument interface or onboard-processing IPUploaded encrypted to a private vaultDetails →
ASIC pathTake the payload chain toward a rad-hard ASIC for constellation volumesASIC Readiness →

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