Conceptual render: a precise three-dimensional library of modular silicon blocks, a few lifted and lit in copper and connected into a small architecture.

140+ IPs · 3rd-party FPGA-proven

140+ 3rd-party FPGA-proven IPs. Selected around your prompt.

From RISC-V processors to a full space IP suite, SIGPT knows what each IP does and how they fit together, and assembles them into your design. Already have proven IP of your own? Bring it, encrypted, and SIGPT stitches it in.

Early Access →Explore the catalogueBring your own IP

Conceptual illustration

01 · Foundation

3rd-party FPGA-proven IP. SIGPT puts it together.

SIGPT reads your prompt, picks matching 3rd-party FPGA-proven IP and wires it into one design.

02Catalogue

140+ IPs across nine families.

Numbered end to end, so you can see the whole portfolio at a glance.

IP 001–005

RISC-V processors

One ISA, five grades. Choosing any of them also generates matching firmware.

5 IPs
  1. 001RISC-V Lite Processor IP
  2. 002RISC-V Standard Processor IP
  3. 003RISC-V Advanced Processor IP
  4. 004RISC-V Automotive-Grade Processor IP
  5. 005RISC-V Space-Grade Processor IP
IP 006–029

Space IP suite

Networking, CCSDS links, coding and fault tolerance.

24 IPs
  1. 006SpaceWire Controller IP
  2. 007SpaceWire Router IP
  3. 008SpaceWire RMAP IP
  4. 009SpaceFibre Controller IP
  5. 010SpaceFibre Router IP
  6. 011SpaceWire Time Distribution Protocol IP
  7. 012CCSDS Telemetry Encoder IP
  8. 013CCSDS Telecommand Decoder IP
  9. 014CCSDS AOS Data Link IP
  10. 015CCSDS Unified Space Data Link Protocol IP
  11. 016CCSDS LDPC Encoder/Decoder IP
  12. 017CCSDS Reed–Solomon Encoder/Decoder IP
  13. 018CCSDS Turbo Encoder/Decoder IP
  14. 019CCSDS 121 Lossless Data Compression IP
  15. 020CCSDS 122 Image Compression IP
  16. 021CCSDS 123 Hyperspectral Image Compression IP
  17. 022CCSDS Space Data Link Security IP
  18. 023CCSDS Optical Communications Coding and Synchronization IP
  19. 024Fault-Tolerant RISC-V Processor IP
  20. 025EDAC Memory Controller IP
  21. 026FPGA Configuration Scrubbing IP
  22. 027Triple Modular Redundancy Voter IP
  23. 028Fault Detection, Isolation and Recovery IP
  24. 029MIL-STD-1553B Controller IP
IP 030–045

PCIe & high-speed

Gen3 to Gen6, plus CXL and UCIe. Controllers support Endpoint and Root Port.

16 IPs
  1. 030PCIe Gen6 Controller IP
  2. 031PCIe Gen5 Controller IP
  3. 032PCIe Gen4 Controller IP
  4. 033PCIe Gen3 Controller IP
  5. 034PCIe Gen6 Switch IP
  6. 035PCIe Gen5 Switch IP
  7. 036PCIe Gen4 Switch IP
  8. 037PCIe Gen3 Switch IP
  9. 038PCIe DMA IP
  10. 039CXL 3.1 Controller IP
  11. 040CXL 3.0 Controller IP
  12. 041CXL 2.0 Controller IP
  13. 042CXL 1.1 Controller IP
  14. 043UCIe 2.0 Die-to-Die Controller IP
  15. 044UCIe 1.1 Die-to-Die Controller IP
  16. 045UCIe 1.0 Die-to-Die Controller IP
IP 046–078

NVMe & storage

Every major version, from host protocols to raw NAND.

33 IPs
  1. 046NVMe 2.1 Host Controller IP
  2. 047NVMe 2.0 Host Controller IP
  3. 048NVMe 1.4 Host Controller IP
  4. 049NVMe 2.1 Device Controller IP
  5. 050NVMe 2.0 Device Controller IP
  6. 051NVMe 1.4 Device Controller IP
  7. 052NVMe Queue Management & DMA IP
  8. 053SATA Gen3 (6 Gb/s) Host Controller IP
  9. 054SATA Gen2 (3 Gb/s) Host Controller IP
  10. 055SATA Gen1 (1.5 Gb/s) Host Controller IP
  11. 056SATA Gen3 (6 Gb/s) Device Controller IP
  12. 057SATA Gen2 (3 Gb/s) Device Controller IP
  13. 058SATA Gen1 (1.5 Gb/s) Device Controller IP
  14. 059AHCI Controller IP
  15. 060UFS 4.1 Host Controller IP
  16. 061UFS 4.0 Host Controller IP
  17. 062UFS 3.1 Host Controller IP
  18. 063UFS 4.1 Device Controller IP
  19. 064UFS 4.0 Device Controller IP
  20. 065UFS 3.1 Device Controller IP
  21. 066eMMC 5.1 Controller IP
  22. 067eMMC 5.0 Controller IP
  23. 068eMMC 4.51 Controller IP
  24. 069SD 7.0 (SD Express) Controller IP
  25. 070SD 4.0 (UHS-II) Controller IP
  26. 071SD 3.0 (UHS-I) Controller IP
  27. 072SDIO 4.10 Controller IP
  28. 073SDIO 3.0 Controller IP
  29. 074ONFI 5.1 NAND Flash Controller IP
  30. 075ONFI 5.0 NAND Flash Controller IP
  31. 076ONFI 4.2 NAND Flash Controller IP
  32. 077NAND Flash BCH ECC IP
  33. 078NAND Flash LDPC ECC IP
IP 079–089

DDR memory

Every DRAM type, kept reliable.

11 IPs
  1. 079DDR3 Controller IP
  2. 080DDR4 Controller IP
  3. 081DDR5 Controller IP
  4. 082LPDDR4 Controller IP
  5. 083LPDDR4X Controller IP
  6. 084LPDDR5 Controller IP
  7. 085LPDDR5X Controller IP
  8. 086HBM Memory Controller IP
  9. 087ECC / EDAC IP
  10. 088Memory Scrubbing IP
  11. 089Memory BIST & Repair IP
IP 090–105

Ethernet & networking

1G to 800G, time-sensitive and fabric-ready.

16 IPs
  1. 0901G Ethernet MAC IP
  2. 09110G Ethernet MAC IP
  3. 09225G Ethernet MAC IP
  4. 09340G Ethernet MAC IP
  5. 09450G Ethernet MAC IP
  6. 095100G Ethernet MAC IP
  7. 096200G Ethernet MAC IP
  8. 097400G Ethernet MAC IP
  9. 098800G Ethernet MAC IP
  10. 099Ethernet Switch IP
  11. 100Time-Sensitive Networking IP
  12. 101IEEE 1588 PTP IP
  13. 102TCP/IP Offload Engine IP
  14. 103UDP/IP Offload Engine IP
  15. 104NVMe-over-Fabrics TCP IP
  16. 105NVMe-over-Fabrics RDMA IP
IP 106–119

On-chip interconnect

The AMBA family, bridges and DMA.

14 IPs
  1. 106AMBA AXI4 IP
  2. 107AMBA AXI4-Lite IP
  3. 108AMBA AXI4-Stream IP
  4. 109AMBA AHB IP
  5. 110AMBA AHB-Lite IP
  6. 111AMBA APB IP
  7. 112AMBA ACE IP
  8. 113AMBA ACE-Lite IP
  9. 114AMBA CHI IP
  10. 115AXI Crossbar & Interconnect IP
  11. 116AXI2AHB Bridge IP
  12. 117AXI2APB Bridge IP
  13. 118AHB2APB Bridge IP
  14. 119DMA Controller IP
IP 120–140

Peripheral interfaces

USB, automotive buses, audio and debug.

21 IPs
  1. 120USB 2.0 Controller IP
  2. 121USB 3.2 Controller IP
  3. 122USB4 Router IP
  4. 123MIPI I3C Controller IP
  5. 124I²C Controller IP
  6. 125SPI Controller IP
  7. 126QSPI Controller IP
  8. 127Octal SPI Controller IP
  9. 128UART IP
  10. 129USART IP
  11. 130CAN Controller IP
  12. 131CAN FD Controller IP
  13. 132CAN XL Controller IP
  14. 133LIN Controller IP
  15. 134I²S Audio Interface IP
  16. 135TDM Audio Interface IP
  17. 136GPIO IP
  18. 137PWM IP
  19. 138Timer IP
  20. 139Watchdog IP
  21. 140JTAG / Debug Interface IP
IP 141–148

Video & multimedia

Capture, code and display.

8 IPs
  1. 141H.264 / AVC Encoder & Decoder IP
  2. 142H.265 / HEVC Encoder & Decoder IP
  3. 143MIPI CSI-2 Camera Interface IP
  4. 144MIPI DSI Display Interface IP
  5. 145MIPI DSI-2 Display Interface IP
  6. 146HDMI Transmitter & Receiver IP
  7. 147DisplayPort Controller IP
  8. 148eDP Controller IP
Breadth is not universal availability. Not every IP is available on every FPGA or configuration. We confirm it for your target.
03Bring your own IP

Your proven IP, stitched with ours.

If you already have proven IP or proven custom logic, you don't have to rebuild it. Upload it encrypted to a private vault that only your organisation can access. SIGPT treats it as a sealed block, connects it to catalogue IP through standard interfaces, builds one bitfile and lets you test it in the Remote FPGA Lab.

Early access

Your IP · encryptedCatalogue IPGenerated by SIGPT
01 · Access

Open a private vault

We check your organisation and set up a vault under a confidentiality agreement. You decide which named users can get in, and every sign-in needs multi-factor authentication.

02 · Upload

Encrypt, then upload

Encrypt your RTL or netlist with standard IEEE 1735 before upload. Add a short interface description and your constraints.

03 · Check

Interface check

SIGPT reads only the ports, parameters, clocks and resets, and confirms they match a supported standard interface. Any mismatch is reported to you before a build is quoted.

04 · Stitch

Stitch and build

Name your block in the prompt. SIGPT selects catalogue IP around it, generates the interconnect, clocks and address map, then runs synthesis, implementation and timing on the whole design.

05 · Test

Prove it on a board

You get a device-locked bitfile. Load it on a reserved board in the Remote FPGA Lab and run your own tests.

What SIGPT sees

A sealed block with known edges.

SIGPT needs your block's edges, not its internals. It reads the interface and wires everything around it. The internal logic stays encrypted during synthesis and implementation, and it never appears in reports, logs or the generated integration code.

Encrypted RTLVerilog, SystemVerilog or VHDLEncrypted with IEEE 1735
NetlistEDIF or a synthesised design checkpointMust target the same FPGA family as the build
InterfacePort list, parameters, clock and reset domainsIP-XACT accepted if you have it
ConstraintsTiming and clock constraints for the block
Tests · optionalYour testbench or on-board test scriptRun by you in the Remote FPGA Lab

Standard interfaces make the join.

AXI4 memory-mappedAXI4-Lite registersAXI4-Stream dataAHB / AHB-LiteAPB peripheralsClock, reset and interrupt

If your block uses a custom bus, SIGPT can wrap it with a bridge to a standard interface, but only once you've confirmed how the bus works. It never guesses.

Protected at every step.

Private to your organisation

Each vault is isolated. Your IP is never shared with other customers or added to the public catalogue.

Never used for training

Your uploaded IP is not used to train or improve SIGPT's models, for you or anyone else.

Encrypted end to end

Your IP is encrypted before upload and stays encrypted in transit and at rest. It is only decrypted inside the isolated build job, never in a readable form.

Named access only

Only users you approve can see the vault, and each sign-in uses multi-factor authentication. Credits and access stay per user.

Every action logged

Uploads, builds and downloads are recorded in an audit log that your administrator can review.

Yours to delete

Remove a block or close the vault at any time. Stored copies are deleted and you get written confirmation.

Before you upload

You prove the block. We prove the join.

  • You confirm your IP is proven and that you have the rights to use itSIGPT integrates your block. It does not re-verify or certify it.
  • SIGPT checks the interface, timing and the full buildYou get integration and timing reports for the combined design.
  • Netlists must match the target FPGA familyEncrypted RTL is more flexible across devices.
  • Board tests are run by you in the Remote FPGA LabThe same by-the-hour lab rates apply.

Ownership and credits

Your IP stays yours.

  • You keep full ownership of your IPOur licence covers only the catalogue IP and the logic SIGPT generates.
  • No catalogue credits are charged for your own blocksPrompts, iterations, catalogue IP and the build fee use credits as usual. See pricing
  • The bitfile is device-locked, like every SIGPT buildA production licence covers the SIGPT parts of the design.
Early access. Private IP vaults are offered to early-access customers on AMD Xilinx targets. Supported formats and interfaces are confirmed for each project before anything is uploaded. Request vault access →
04Prompt to architecture

How a sentence becomes a selection.

Reusable IPGenerated by SIGPT
See this use case →
05Precise language

We say exactly what has been proven.

3rd-party FPGA-proven

Proven on FPGA

Every IP in the 140+ catalogue is 3rd-party FPGA-proven IP.

FPGA-validated

Built and tested on FPGA

Your design is built and validated on your target FPGA.

Compatible

Confirmed per project

Checked against your device and board.

Customer-proven

Proven by you

Your own IP, proven by you. SIGPT checks the interface, not the internals.

Tell us the function. We’ll find the blocks.

Early Access →