Conceptual render: glowing prompt traces resolving into machined IP blocks, which settle into an FPGA package on a dark board.

From a simple prompt to a device-locked FPGA bitfile.

Type a simple prompt. FPGA Build selects compatible IP, integrates it, runs synthesis, implementation and timing for your registered device, and delivers a device-locked bitfile, plus matching firmware when your design includes a RISC-V processor, to test in the Remote FPGA Lab, then license it for FPGA production or take the ASIC path.

Build Your First FPGA Project →See the full workflow

Conceptual illustration

CapabilitiesAvailable today

Six steps, one engagement.

01 · Input

A simple prompt

Say what you want built in a sentence or two, the way you'd ask a colleague. SIGPT works out the details and asks only if something is unclear.

02 · Selection

Compatible IP selection

Functions are mapped to 140+ 3rd-party FPGA-proven IPs that suit your target device and the configuration you need. You can also add your own proven IP.

03 · Assembly

Configuration and integration

IP is parameterised, and interconnect, clocks, resets and registers are generated to join the blocks into one system.

04 · Implementation

Target-specific build

Checks, synthesis and implementation run for the exact registered FPGA part, whether on a supported board or your custom one.

05 · Delivery

Device-locked bitstream

You receive a bitstream licensed and bound to the registered FPGA device. If the design has a RISC-V, you also get matching firmware.

06 · Proof

Test in the Remote FPGA Lab

Use a ZCU106, KCU116 or Zybo Z7-20 in the Remote FPGA Lab, available 24/7 from $5/hr, or use your own board. Board validation is a separate milestone from delivery.

FirmwareFor RISC-V designs

Hardware and firmware, from one prompt.

When your prompt includes any RISC-V processor, FPGA Build generates the firmware along with the RTL. Both come from the same specification, so register addresses, interrupts and clocks always match.

What's generated

A full stack, sized to your prompt.

Firmware is implicit, so you never have to ask for it. Every RISC-V design gets the standard layers. Application logic is added only for behaviour your prompt describes: a list of IP gives you drivers and a self-test, while “prioritise downlink” gives you a scheduler.

Standard · every RISC-V designFrom your prompt · only what you describe
05Application
The behaviour you described, with clear places to extend it.
04RTOS or bare-metal
Chosen from your timing and concurrency needs.
03Drivers
One per selected IP, such as SPI, I²C, DMA, Ethernet, NVMe or SpaceFibre.
02Board support
Register headers and interrupt map, generated from the RTL spec.
01Boot & startup
Reset vector, clock setup, linker script and memory map.
+Build & debug
Makefile, standard RISC-V GCC toolchain and a JTAG debug configuration.
Supported

Every RISC-V grade

Lite, Standard, Advanced, Automotive-grade, Space-grade and Fault-tolerant RISC-V in the catalogue. Toolchain flags and startup code match the core you selected.

Tested

Proven on a board

In the Remote FPGA Lab, you program the bitfile, load the firmware over JTAG and watch the UART console. You can also replace it with your own build at any time.

Credits

Priced by complexity

Firmware uses credits based on its complexity and code length. A small driver set costs little, a full RTOS application costs more. See pricing

Generated, then tested on hardware. Generated firmware is a working starting point that SIGPT tests with your design in the lab. It is not certified for safety or flight use. Production rights for the firmware are covered by the production licence or source purchase.
Your IPEarly access

Build around the logic you already trust.

Bring your proven IP or custom logic to a private, encrypted vault. FPGA Build treats it as a sealed block, connects it to catalogue IP through standard interfaces and builds the whole design as one device-locked bitfile.

Example prompt

“Connect my_filter_v3 to the host over PCIe, buffered in DDR4.”

SIGPT finds my_filter_v3 in your vault and reads its AXI4-Stream and AXI4-Lite ports. It picks PCIe, DMA and DDR4 from the catalogue and generates the interconnect, clocks and CDC. Then it builds and times the whole design for your registered device.

Your IP · encryptedCatalogue IPGenerated
01 · Vault

Private, encrypted upload

Upload IEEE 1735 encrypted RTL or a netlist, with its interface and constraints. The vault is isolated to your organisation, open only to named users with multi-factor authentication, and your IP is never used for training.

02 · Interface check

Checked before quoting

SIGPT reads ports, parameters, clocks and resets, and matches them to AXI4, AXI4-Lite, AXI4-Stream, AHB or APB. Any mismatch is reported before a build is quoted.

03 · Stitch

One design, one build

Your block goes in as a black box. Integration logic is generated around it, and synthesis, implementation and timing run on the full design.

04 · Reports

Integration you can inspect

You get resource and timing reports for the combined design. The internals of your block stay encrypted and never appear in reports or logs.

05 · Proof

Test in the Remote Lab

Load the device-locked bitfile onto a reserved board in the Remote FPGA Lab and run your own tests against it.

06 · Ownership

Your IP stays yours

You keep full ownership of your IP. There are no catalogue credits for your own blocks, but prompts, catalogue IP and the build fee use credits as usual. Licensing covers only the SIGPT parts of the design.

You prove the block. We prove the join. You confirm your IP is proven and that you have the rights to use it. SIGPT checks integration and timing, not your block's internal function. Netlists must match the target FPGA family. Full details →

What you see

Every project, one clear record.

Each project gets a single summary tracking requirements, the IP chosen, the target and the status of both milestones. The example on the right is illustrative. Its fields show structure, not real results.

Deliverables and licensing. FPGA Build delivers a device-locked evaluation bitfile for testing. Once you're happy, you can optionally buy a production licence for the bitfile or the full project source code, or take the ASIC path.

Project: Custom PCIe accelerator interface

Illustrative
Functional requirements
Your AXI-Stream module integrated · host data in over PCIe · DDR4 buffering · results returned · throughput and latency measured
Selected IP
PCIe controllerDMA engineDDR4 controllermy_accel_axis · your IP, encryptedRegisters · generatedIntegration · generated
Your IPInterface check: AXI4-Stream, AXI4-Lite
Target board / device
KCU116 · AMD · in the Remote FPGA Lab
Build statusShown per project
Resource & timingReports attached where available
FirmwareGenerated when a RISC-V is in the design
Bitstream deliveryDevice-locked to registered FPGA
Board validationRemote FPGA Lab · reserved by the hour
LicenceEvaluation → production licence or source code
TargetsWhere it runs

Supported board or your own.

AMD FPGAs are supported today, from the three boards in our lab to any standard commercial AMD board or your own custom board. More vendors are coming.

Vendor todayAMD FPGAsAvailable
In the Remote LabAMD ZCU106 · AMD KCU116 · Digilent Zybo Z7-20Build and test by the hourBoards →
Commercial boardsAny standard AMD FPGA boardNot listed? Request it and we'll add itFind yours →
Custom boardsPrivate custom-board profilePart, pins, clocks, memory and interfaces, visible only to your accountDetails →
Your own IPEncrypted RTL or netlist, from a private vaultStitched through AXI4, AXI4-Lite, AXI4-Stream, AHB or APBEarly access
Other vendorsAdditional FPGA vendorsComing soon

Your first build starts with a paragraph.

Tell us what you want to build and which board it runs on.

Build Your First FPGA Project →Request vault access