Conceptual render: a ruggedised data-recorder enclosure with industrial Ethernet cables and an NVMe drive caddy.

Example project · UC 07

Record every sample. Miss nothing.

An example project that turns an FPGA board into a continuous data recorder for industrial test: Ethernet in, DDR4 burst buffer, NVMe SSD out.

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Conceptual illustration

The problem

Test rigs produce bursts faster than a PC can reliably write them.

Industrial test systems stream timestamped sensor data in bursts. A PC-based recorder can drop samples under load, and nobody notices until the analysis is wrong. A hardware recorder needs Ethernet ingest, deep buffering, sustained SSD writes and honest reporting of any gaps.

OutcomeContinuous recording with missing-sample detection and speed and overrun reporting.
TargetCommercial or custom AMD board with Ethernet, DDR4 and an NVMe SSD interface

The prompt

The simple prompt
Build an FPGA data recorder for my industrial test system. Receive timestamped sensor data over Ethernet, buffer traffic bursts in DDR4 and continuously record to an NVMe SSD. Detect missing samples and report sustained recording speed and buffer overruns.

An example request. Compatibility and availability are confirmed for each selected configuration.

ArchitectureConceptual

A simple conceptual architecture.

High-Speed Industrial Data RecorderConceptual block diagram · not a delivered netlist
ExternalReusable IPGenerated logic
Good to know. The sustained recording speed depends on the SSD, the board interface and the traffic profile. It is measured on your setup.

IP needed

What SIGPT would assemble.

Selected from 140+ 3rd-party FPGA-proven IPs.

Ethernet & networkingEthernet MAC IP
DDR memory interfacesDDR4 controller IP as burst buffer
NVMe & storageNVMe host controller IP
Generated logicSample checker, record scheduler, statistics registers

Validation steps

How it would be proven on hardware.

Board validation is its own milestone, separate from bitfile generation. Any results are measured on your setup, and none are shown here.

No board? Use the Remote FPGA Lab. Ask for a custom lab setup with the interfaces this design needs, or prove the core logic on a bare lab board, available 24/7 from $5/hr, then license it for FPGA production or take the ASIC path. Remote Lab →
  1. Program the bitfile and connect the sensor network and NVMe SSD.
  2. Stream timestamped test data at the expected burst profile.
  3. Confirm continuous recording and check the missing-sample report.
  4. Read sustained recording speed and buffer-overrun counters.
  5. Compare results with the agreed acceptance criteria.

Start from this prompt. Make it yours.

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