Conceptual render: two machine-vision cameras on a bracket, cabled to an FPGA acquisition card.

Example project · UC 04

Two cameras. One synchronised view.

An example project for factory inspection: synchronised dual-camera capture, region-of-interest cropping, DDR4 buffering and PCIe transfer to the host.

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Conceptual illustration

The problem

Inspection needs frames that line up in time.

Factory inspection often combines two viewpoints. If frames are not captured together, measurements disagree. Sending full frames also wastes bandwidth when only one inspection region matters.

OutcomeSynchronised, cropped frames delivered to the host with drop and alignment reporting.
TargetCustom or commercial Xilinx board with two camera interfaces and PCIe

The prompt

The simple prompt
Build a dual-camera acquisition pipeline for a factory inspection system. Synchronise frame capture, crop each image to a configurable inspection region, buffer frames in DDR4 and transfer them to the host over PCIe. Report dropped frames and timestamp alignment.

An example request. Compatibility and availability are confirmed for each selected configuration.

ArchitectureConceptual

A simple conceptual architecture.

Multi-Camera Acquisition CardConceptual block diagram · not a delivered netlist
ExternalReusable IPGenerated logic
Good to know. Camera interface type, lane count and resolution depend on the sensors and board, and are confirmed for your configuration.

IP needed

What SIGPT would assemble.

Selected from 140+ 3rd-party FPGA-proven IPs.

Video & multimediaCamera receiver IP ×2, video DMA
DDR memory interfacesDDR4 controller IP as frame buffer
PCIe & high-speed connectivityPCIe controller IP
Generated logicFrame synchroniser, ROI cropper, timestamp alignment monitor

Validation steps

How it would be proven on hardware.

Board validation is its own milestone, separate from bitfile generation. Any results are measured on your setup, and none are shown here.

No board? Use the Remote FPGA Lab. Ask for a custom lab setup with the interfaces this design needs, or prove the core logic on a bare lab board, available 24/7 from $5/hr, then license it for FPGA production or take the ASIC path. Remote Lab →
  1. Connect both cameras and program the bitfile.
  2. Trigger synchronised capture and set an inspection region.
  3. Confirm cropped frames arrive at the host over PCIe.
  4. Check the dropped-frame counter and the timestamp alignment between cameras.
  5. Compare results with the agreed acceptance criteria.

Start from this prompt. Make it yours.

We’ll prefill your request with this use case. Edit it to match your requirements.

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