Your FPGA prototype can be the beginning of your silicon journey.
The ASIC path. After you've tested your bitfile in the Remote FPGA Lab, you can license it for FPGA production or take the ASIC path. ASIC Readiness takes the validated FPGA design and prepares it for ASIC implementation: portable, better verified and clearly scoped.
Conceptual illustration
WorkflowSix steps
Six steps from prototype to package.
The steps below describe how ASIC Readiness takes a validated FPGA design toward an ASIC design package. Scope is agreed with you for each project.
- Review the validated architectureStart from a design that has passed board validation, and record its requirements and structure.
- Identify FPGA-specific dependenciesFind vendor primitives, clocking resources, memories and I/O that have no direct ASIC equivalent.
- Prepare portable RTL and suitable IP configurationsMove toward technology-independent design and IP settings suited to ASIC targets, subject to licence.
- Extend verificationBroaden verification beyond FPGA validation to the coverage expected for silicon.
- Prepare constraints and design collateralTiming constraints, interface definitions and documentation for the implementation team.
- Scope process-specific requirementsIdentify the memories, PHYs, DFT and implementation work needed for the chosen process.
Scope
Preparation is not tapeout.
A working FPGA bitstream does not automatically become a production chip. ASIC Readiness is about preparing a design package. Physical design, sign-off and fabrication are separate engineering work.
In scope
ASIC design preparation
- Architecture review from a validated prototype
- Portability analysis and RTL preparation
- Extended verification planning
- Constraints and collateral
- Scoping of process-specific IP, PHYs and DFT
Outside this workflow
Completed silicon implementation
- Physical design and place-and-route
- Timing, power and physical sign-off
- Foundry engagement and tapeout
- Silicon bring-up and qualification
Talk to us early. If you register interest, we can talk through your design, target process and timing needs, and scope an ASIC Readiness engagement with you.