Conceptual render: a PCIe network card with optical transceivers and fibres catching light.

Example project · UC 03

Capture the packets that matter.

An example project that offloads packet filtering, timestamping and flow distribution from the host of a network-monitoring appliance.

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Conceptual illustration

The problem

Software capture falls behind as links get faster.

Monitoring appliances need to keep only the traffic that matters, timestamp it precisely and keep each flow on one host queue so analysis software sees packets in order. Doing this in software costs CPU and drops packets under load.

OutcomeHardware filtering, timestamping and flow-consistent queueing with capture statistics.
TargetCommercial or custom AMD board with SFP+/Ethernet and PCIe

The prompt

The simple prompt
Build a packet-capture accelerator for my network-monitoring appliance. Filter traffic by IP address, port and VLAN, timestamp selected packets and distribute each flow consistently across host receive queues. Report capture rate, queue occupancy and packet drops.

An example request. Compatibility and availability are confirmed for each selected configuration.

ArchitectureConceptual

A simple conceptual architecture.

Network Packet-Capture AcceleratorConceptual block diagram · not a delivered netlist
ExternalReusable IPGenerated logic
Good to know. Line rate depends on the board’s physical Ethernet interface and PCIe link, and is confirmed for your configuration.

IP needed

What SIGPT would assemble.

Selected from 140+ 3rd-party FPGA-proven IPs.

Ethernet & networkingEthernet MAC IP
PCIe & high-speed connectivityPCIe controller IP
Data movementMulti-queue DMA engine IP
Generated logicPacket filter, timestamp unit, flow-hash distributor, capture statistics

Validation steps

How it would be proven on hardware.

Board validation is its own milestone, separate from bitfile generation. Any results are measured on your setup, and none are shown here.

No board? Use the Remote FPGA Lab. Ask for a custom lab setup with the interfaces this design needs, or prove the core logic on a bare lab board, available 24/7 from $5/hr, then license it for FPGA production or take the ASIC path. Remote Lab →
  1. Install the board in the appliance host and program the bitfile.
  2. Replay known traffic with a mix of IPs, ports and VLANs.
  3. Confirm only matching packets are captured and timestamped.
  4. Check that each flow always lands on the same host queue.
  5. Read capture rate, queue occupancy and drop counters.

Start from this prompt. Make it yours.

We’ll prefill your request with this use case. Edit it to match your requirements.

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