Conceptual render: a compact FPGA board wired to sensor modules, with an NVMe SSD and Ethernet cable, under copper rim light.

Example project · UC 01

A complete logging system. On one FPGA.

An example project that turns a single FPGA into a smart data logger. A RISC-V processor samples sensors over SPI, I²C and GPIO, buffers data in DDR, records to an NVMe SSD and streams live over 1G Ethernet.

Apply With This Use Case →

Conceptual illustration

The problem

Field loggers are usually a microcontroller plus a PC plus glue.

Typical data loggers split the work across a microcontroller for the sensors, a separate storage path and a PC for networking. Each extra piece adds latency, cost and a place where samples can go missing. Putting a processor, sensor interfaces, memory, storage and networking on one FPGA gives a small, deterministic system that you can still program in software.

OutcomeA RISC-V system on one FPGA that timestamps sensor samples, records them to NVMe and streams or serves them over Ethernet.
TargetCommercial or custom AMD board with sensor headers, DDR, 1G Ethernet and an M.2 or PCIe NVMe slot

The prompt

The simple prompt
Build an FPGA-based smart data logger using a RISC-V processor integrated with SPI, I²C, GPIO, timer, AXI interconnect, DMA, DDR memory controller, 1Gb Ethernet MAC and PCIe/NVMe host IPs.

An example request. Compatibility and availability are confirmed for each selected configuration.

RequirementsRead from the prompt

What SIGPT reads into it.

The prompt names the IP directly. SIGPT turns it into a working system: what each block is for and how they connect.

01 · Processor

RISC-V control plane

Runs the logging application, configures peripherals and manages files and the network. SIGPT picks a grade that fits the device and your throughput needs.

02 · Sensors

SPI, I²C and GPIO capture

Sensor buses and discrete inputs, with pins taken from the board profile. The timer sets sample rates and provides timestamps.

03 · Data movement

AXI and DMA

An AXI interconnect joins the processor and peripherals. DMA moves sample blocks to DDR without loading the CPU.

04 · Buffering

DDR memory controller

DDR holds program memory and a log buffer that absorbs bursts while the SSD writes.

05 · Storage

PCIe / NVMe host

Continuous log recording to an NVMe SSD over PCIe. The data path is sized from your sample rates.

06 · Network

1G Ethernet MAC

Live streaming, remote configuration and log download over a standard network.

ArchitectureConceptual

A simple conceptual architecture.

RISC-V Smart Data LoggerConceptual block diagram · not a delivered netlist
ExternalReusable IPGenerated logic
Good to know. Sustained logging rates depend on the sensors, the SSD, the Ethernet traffic and the software running on the RISC-V. They are measured on your setup. Generated firmware is a standard stack plus a basic logging loop. See Firmware below.
FirmwareImplicit with RISC-V

The prompt names a RISC-V. The firmware comes with it.

You don’t have to ask for firmware. Because the prompt includes a RISC-V, SIGPT generates a standard firmware stack for it automatically. Most of this prompt is a list of IP, so the firmware stays standard except for one functional phrase.

Always generated

Standard firmware stack

  • Boot and startup codeReset vector, clock and memory setup, linker script
  • Board support packageRegister headers and interrupt map, from the same spec as the RTL
  • A driver for every selected IPInit, read, write, interrupt and DMA hooks
  • Bring-up self-testChecks each peripheral and memory at power-on
  • UART console and JTAG debugStatus, register peek and poke, and logs
  • Build filesMakefile and standard RISC-V GCC toolchain
Added from this prompt

A basic logging loop

  • smart data loggerThe only function the prompt describes, so SIGPT adds a simple logging loop
  • Read each sensor on a timer tickDefault rate, configurable from the console
  • Timestamp samples and write records to NVMe via DMASimple fixed-size record format
  • Live stream over 1G EthernetBasic UDP output
Want more specific firmware? Describe it in the prompt and SIGPT generates it. For example: sample the I²C sensors at 1 kHz, store CSV files rotated hourly, and serve them over HTTP. Anything you don’t describe stays standard.

IP needed

What SIGPT would assemble.

Selected from 140+ 3rd-party FPGA-proven IPs. Eleven IP blocks, all named in the prompt.

RISC-V processorsRISC-V processor IPGrade chosen for the target device
Peripheral interfacesSPI, I²C, GPIO and Timer IP
On-chip interconnectAXI crossbar & interconnect IP, DMA controller IP
DDR memoryDDR4 controller IPOr DDR3 or LPDDR, depending on the board
Ethernet & networking1G Ethernet MAC IP
PCIe & storagePCIe controller IP, NVMe host controller IP
Generated firmwareStandard stack: boot, BSP, drivers for SPI, I²C, GPIO, timer, DMA, Ethernet and NVMe, self-test and console, plus a basic logging loopImplicit with RISC-V · details
Generated logicSample timestamping, log formatter, memory map and boot configuration

Validation steps

How it would be proven on hardware.

Board validation is its own milestone, separate from bitfile generation. Any results are measured on your setup, and none are shown here.

No board? Use the Remote FPGA Lab. Start on the Zybo Z7-20 in the Remote FPGA Lab, available 24/7 at $5/hr, or ask for a custom setup with sensors and an NVMe drive connected. Remote Lab →
  1. Program the bitfile, load the generated firmware and check the self-test results on the UART console.
  2. Connect SPI and I²C sensors and GPIO inputs, and confirm each one is sampled at its configured rate.
  3. Record continuously to the NVMe SSD and check timestamps and sequence numbers for gaps.
  4. Stream live data and download logs over 1G Ethernet.
  5. Compare sample rates, recording continuity and network behaviour with the agreed acceptance criteria.
NextAfter the lab

From lab bench to fleet.

Once the logger passes in the lab, choose how to take it further.

FPGA productionLicense the bitfile or buy the full project sourceFor deployment on your registered devicesLicensing →
Your own IPAdd your own proven sensor-processing or filtering logic next to the RISC-VUploaded encrypted to a private vaultDetails →
ASIC pathTake the RISC-V system toward an SoC for high-volume loggersASIC Readiness →

Start from this prompt. Make it yours.

We’ll prefill your request with this use case. Edit it to match your requirements.

Apply With This Use Case →All use cases