Conceptual render: an FPGA accelerator card being seated into a PCIe slot.

Example project · UC 05

Bring your module. We build the accelerator.

An example project that wraps your own AXI-Stream processing module with PCIe, DMA, DDR4 buffering, control registers and performance counters.

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Conceptual illustration

The problem

Your algorithm is ready; the plumbing is not.

Teams often have a working processing core but spend weeks on the host interface: PCIe, DMA, buffering, registers and measurement. SIGPT builds that infrastructure around your module so you can focus on the algorithm.

OutcomeYour module running as a PCIe accelerator with measured throughput and latency.
TargetKCU116 in the Remote FPGA Lab, or any AMD board with PCIe and DDR4

The prompt

The simple prompt
Integrate my AXI-Stream processing module into a PCIe accelerator. Move input data from host memory through the module and return the results, using DDR4 for buffering. Add control registers and measure end-to-end throughput and latency.

An example request. Compatibility and availability are confirmed for each selected configuration.

ArchitectureConceptual

A simple conceptual architecture.

Custom PCIe Accelerator InterfaceConceptual block diagram · not a delivered netlist
ExternalReusable IPGenerated logic
Good to know. Your module is integrated as supplied. Its own timing and resource use affect the final build, and are reported where available.

IP needed

What SIGPT would assemble.

Selected from 140+ 3rd-party FPGA-proven IPs.

PCIe & high-speed connectivityPCIe controller IP
Data movementDMA engine IP
DDR memory interfacesDDR4 controller IP
Generated logicAXI-Stream wrapper, control/status registers, performance counters

Validation steps

How it would be proven on hardware.

Board validation is its own milestone, separate from bitfile generation. Any results are measured on your setup, and none are shown here.

No board? Use the Remote FPGA Lab. Ask for a custom lab setup with the interfaces this design needs, or prove the core logic on a bare lab board, available 24/7 from $5/hr, then license it for FPGA production or take the ASIC path. Remote Lab →
  1. Share your AXI-Stream module and program the generated bitfile.
  2. Send known input data from host memory through the module.
  3. Compare returned results with your reference output.
  4. Read end-to-end throughput and latency from the performance counters.
  5. Record results against the agreed acceptance criteria.

Start from this prompt. Make it yours.

We’ll prefill your request with this use case. Edit it to match your requirements.

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