Conceptual render: a sequence of machined graphite tiles linked by a continuous copper trace, each one a step further from blank sheet to finished board.

Build · Test · FPGA Production or ASIC Path

From a simple prompt to a device-locked bitfile.

Type one or two sentences. SIGPT handles the engineering, using our 140+ IPs and, if you have it, your own proven IP: IP selection, integration, synthesis, implementation, timing and bitfile generation, plus matching firmware if your design includes a RISC-V. You test on real boards in the Remote FPGA Lab, then license it for FPGA production or take the ASIC path.

Early Access →

Conceptual illustration

WorkflowNine steps

What happens, step by step.

Step Milestone Flow Review loop
FirmwareRISC-V designs

A RISC-V in the prompt adds a firmware track.

When SIGPT finds a RISC-V processor in your prompt, it starts a second track alongside the hardware. It uses the same spec to generate firmware that matches, then delivers both together.

  1. 02
    Dissect

    The prompt's behaviour is split into hardware functions and software tasks.

  2. 03–04
    Select and integrate

    As the RTL is wired up, the memory map, interrupts and clocks are fixed. The firmware uses the same values.

  3. 04b
    Generate firmware

    Boot code, board support, drivers for each selected IP, an optional RTOS and the application, compiled for your RISC-V grade.

  4. 06
    Deliver

    A device-locked bitfile and a matching firmware image, with sources and build files.

  5. 07
    Validate

    Boot both together on a Remote Lab board and check the console.

Firmware uses credits based on its complexity and code length. See pricing →

Your IPEarly access

Your proven logic runs through the same flow.

Already have proven IP or custom logic? Upload it encrypted to a private vault. From then on it moves through every step alongside our IP, as a sealed block that SIGPT connects but never opens.

  1. 00
    Upload once

    Encrypted RTL or netlist, plus its interface and constraints, goes into a vault only your organisation can access.

  2. 01
    Prompt

    Name your block in the prompt, like connect my_filter_v3 to the host over PCIe.

  3. 03
    Select IP

    SIGPT picks catalogue IP around your block. It doesn't duplicate what you already have.

  4. 04
    Integrate

    Your ports are checked against AXI4, AXI4-Lite, AXI4-Stream, AHB or APB, and the glue logic is generated around them.

  5. 05–06
    Build and deliver

    The whole design is synthesised, timed and locked to your device. Reports never show your block's internals.

  6. 07
    Validate

    Run your own tests on a real board in the Remote FPGA Lab.

You prove the block. We prove the join. SIGPT checks integration and timing, not your block's internal function. Your IP stays yours, is never used for training, and costs no catalogue credits. Full details →

Two milestones

A bitstream is not a validated design.

Milestone 1

Bitstream generated

Built and timing-closed for your FPGA.

Proves it builds.
Milestone 2

Board validation

Runs on a real board and passes your tests.

Proves it works.
ReviewWhen things are unclear

Ambiguity is a question, not a guess.

Unclear

We ask

Missing details get a specific question.

Unsupported

We flag it

Out-of-scope needs go to engineering review.

Board limits

We check the board

Link speeds and PHYs must match the hardware.

Bring a requirement. We’ll take it from there.

Stages 01 to 08 are available today: build, Remote Lab testing and licensing on supported AMD Xilinx targets.

Early Access →FPGA Build details